SHA256d Hash Rate Enhancement by L3 Cache

被引:0
作者
Takahashi, Hironao [1 ]
Nakano, Shinji [2 ]
Lakhani, Uzair [2 ]
机构
[1] Szabist Univ, Dept Comp Sci, Block 5 Clifton, Karachi, Pakistan
[2] ARIS Inc, Taitou Ku, 1-2-13 Komagata, Tokyo, Japan
来源
2018 IEEE 7TH GLOBAL CONFERENCE ON CONSUMER ELECTRONICS (GCCE 2018) | 2018年
关键词
SHA-2; Blockchain; Thread level Parallelism; L3; cache;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
SHA-2 (Secure Hash Algorithm 2) is a set of cryptographic hash functions designed by the United States National Security Agency (NSA). It has a one way compression function using the Davies-Meyer structure from a (classified) specialized block cipher. SHA-2 is utilized in secured network communications, blockchain applications etc. The mining ware of crypto currency also applies SHA-2 today. To enhance the hash rate computation power, the type of processor is changed from CPU to GPU and ASIC for different currencies. But, the issues are too much energy consumption and heavy heat from processing units. This paper's approach to enhance the hash rate computation is with higher efficiency computer resource management by L3 cache. SHA 2 application generates hash block continuously and store the block in to nearest register or cache memory. But multiple thread process configuration might create instruction stall by cache miss. We implemented L3 cache layer in the code of SHA 2 mining ware and designed higher Thread level Parallelism (TLP) inside. The result shows 531.54% higher than original mining ware program.
引用
收藏
页码:849 / 850
页数:2
相关论文
共 2 条
  • [1] Takahashi Hironao, 2012, ELECT PREPRINT J INF, V20
  • [2] Takahashi Hironao, 2008, 11 IEEE HIGH ASS SYS