Power/performance advantages of victim buffer in high-performance processors

被引：5

作者：

Albera, G ^{[1
]}

Bahar, RI ^{[1
]}

机构：

[1] Politecn Torino, Dipartimento Automat & Informat, I-10129 Turin, Italy

来源：

IEEE ALESSANDRO VOLTA MEMORIAL WORKSHOP ON LOW-POWER DESIGN, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/LPD.1999.750402

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we propose several different data cache configurations and analyze their power as well as performance implications on the processor. Unlike most existing work in low power microprocessor design, we explore a high performance processor with the latest innovations for performance. Using a detailed, architectural-level simulator, we evaluate full system performance using several different power/performance sensitive cache configurations. We then use the information obtained from the simulator to calculate the energy consumption of the memory hierarchy of the system. We show that victim buffer offers improved cache energy consumption over other techniques (10% compared to 3.8%), while at the same time provides comparable performance gains(3.54% compared to 3.45%).

引用

页码：43 / 51

页数：9

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