Time-Domain Multi-bit ΔΣ Analog-to-Digital Converter

被引：2
|
作者：
Kuribayashi, Kazuki [1 ]
Machida, Kazuya [1 ]
Toyama, Yuji [1 ]
Waho, Takao [1 ]
机构：
[1] Sophia Univ, Dept Informat & Commun Sci, Chiyoda Ku, Tokyo 1028554, Japan
来源：
2011 41ST IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL) | 2011年
关键词：
CONVERSION;
D O I：
10.1109/ISMVL.2011.31
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
A multi-bit representation in the time domain has been applied to a Delta Sigma analog-to-digital converter (ADC), which consists of an asynchronous Delta Sigma modulator (ADSM) and a time-to-digital converter (TDC). Current-mode circuits are included in the ADSM to suppress the variation in the node voltage. The TDC is based on a ring oscillator-based TDC comprised of four stages of differential delay element followed by a counter and a phase detector. The 1st-order noise-shaping was experimentally obtained for the TDC fabricated by using 0.18-mu m standard CMOS technology. A successful operation of the ADC has been obtained by transistor-level circuit simulation.
引用
收藏
页码：254 / 258
页数：5
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