Double pocket architecture using indium and boron for sub-100 nm MOSFETs

被引：5

作者：

Odanaka, S ^{[1
]}

Hiroki, A ^{[1
]}

Yamashita, K ^{[1
]}

Nakanishi, K ^{[1
]}

Noda, T ^{[1
]}

机构：

[1] Matsushita Semicond Co, ULSI Proc Technol Dev Ctr, Kyoto 6018413, Japan

来源：

IEEE ELECTRON DEVICE LETTERS | 2001年 / 22卷 / 07期

关键词：

indium diffusion; junction leakage current; MOSFET; pocket profile;

D O I：

10.1109/55.930681

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A double pocket architecture for sub-100 nm MOSFET's is proposed on the basis of indium pocket profiling at higher hose than the amorphization threshold. At high dose, the low-energy indium pockets realize the improvement of short channel effects and shallow extension formation of highly doped drain, maintaining the low junction leakage level. Double pocket architecture using indium and boron is demonstrated in a 70 nm gate length MOSFET with high drive currents and good control of the short channel effects.

引用

页码：330 / 332

页数：3

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