The FE-I4 pixel readout integrated circuit

被引：201

作者：

Garcia-Sciveres, M. ^{[1
]}

Arutinov, D. ^{[3
]}

Barbero, M. ^{[3
]}

Beccherle, R. ^{[6
]}

Dube, S. ^{[1
]}

Elledge, D. ^{[1
]}

Fleury, J. ^{[2
]}

Fougeron, D. ^{[4
]}

Gensolen, F. ^{[4
]}

Gnani, D. ^{[1
]}

Gromov, V. ^{[5
]}

Hemperek, T. ^{[3
]}

Karagounis, M. ^{[3
]}

Kluit, R. ^{[5
]}

Kruth, A. ^{[3
]}

Mekkaoui, A. ^{[1
]}

Menouni, M. ^{[4
]}

Schipper, J. -D. ^{[5
]}

机构：

[1] Univ Calif Berkeley, Lawrence Berkeley Lab, Berkeley, CA 94720 USA

[2] Lab Accelerateur Lineaire, F-91405 Orsay, France

[3] Univ Bonn, D-5300 Bonn, Germany

[4] Ctr Phys Particules Marseille, Marseille, France

[5] Natl Inst Subatomaire Fys, Amsterdam, Netherlands

[6] Ist Nazl Fis Nucl, Sez Genova, I-16146 Genoa, Italy

来源：

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT | 2011年 / 636卷

关键词：

Pixel detector; ATLAS upgrades; High luminosity; 130; nm;

D O I：

10.1016/j.nima.2010.04.101

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening. (C) 2010 Elsevier B.V. All rights reserved.

引用

页码：S155 / S159

页数：5

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