On-chip interconnect modeling by wire duplication

被引：7

作者：

Zhong, G ^{[1
]}

Koh, CK ^{[1
]}

Roy, K ^{[1
]}

机构：

[1] Purdue Univ, Dept Elect & Comp Engn, W Lafayette, IN 47907 USA

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2003年 / 22卷 / 11期

关键词：

circuit; inductance; interconnect; modeling;

D O I：

10.1109/TCAD.2003.818303

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The authors present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L-1 matrix, where L is the inductance matrix, and constructs a sparse and stable equivalent circuit by windowing the original inductance matrix. The resulting circuit model is sparse and exhibits the same stability property as the K method. Numerical results show that the proposed wire duplication model has high accuracy and is more efficient than many existing techniques.

引用

页码：1521 / 1532

页数：12

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