A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation

被引：9

作者：

Asghar, Sohail ^{[1
,2
]}

Afridi, Sohaib Saadat ^{[1
]}

Pillai, Anu ^{[3
]}

Schuler, Anita ^{[3
]}

de la Rosa, Jose M. ^{[2
]}

O'Connell, Ivan ^{[3
]}

机构：

[1] ROHM Powervat Ltd, Cork T12X N4V, Ireland

[2] Univ Seville, CSIC, IMSE CNM, Seville 41092, Spain

[3] Tyndall Natl Inst, MCCI, Cork T12R 5CP, Ireland

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2018年 / 65卷 / 11期

关键词：

Analog-to-digital converters; SAR; comparator offset; capacitor segmentation; feedback control system; CMOS;

D O I：

10.1109/TCSI.2018.2852761

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 Vpp-d (+/- 1.33 V-REF). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-mu m CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB.

引用

页码：3628 / 3638

页数：11

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