Temperature and supply voltage aware performance and power modeling at microarchitecture level

被引:181
作者
Liao, WP [1 ]
He, L
Lepak, KM
机构
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
[2] Adv Micro Devices Inc, Austin, TX 78741 USA
基金
美国国家科学基金会;
关键词
floorplan; leakage power; microarchitecture; temperature; thermal management;
D O I
10.1109/TCAD.2005.850860
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Performance and power are two primary design issues for systems ranging from server computers to handbelds. Performance is affected by both temperature and supply voltage because of the temperature and voltage dependence of circuit delay. Furthermore, as semiconductor technology scales down, leakage power's exponential dependence on temperature and supply voltage becomes significant. Therefore, future design studies call for temperature and voltage aware performance and power modeling. In this paper, we study microarchitecture-level temperature and voltage aware performance and power modeling. We present a leakage power model with temperature and voltage scaling, and show that leakage and total energy vary by 38% and 24%, respectively, between 65 degrees C and 110 degrees C. We study thermal runaway induced by the interdependence between temperature and leakage power, and demonstrate that without temperature-aware modeling, underestimation of leakage power may lead to the failure of thermal controls, and overestimation of leakage power may result in excessive performance penalties of up to 5.24%. All of these studies underscore the necessity of temperature-aware power modeling. Furthermore, we study optimal voltage scaling for best performance with dynamic power and thermal management under different packaging options. We show that dynamic power and thermal management allows designs to target at the common-case thermal scenario among benchmarks and improves performance by 6.59% compared to designs targeted at the worst case thermal scenario without dynamic power and thermal management. Additionally, the optimal V-dd for the best performance may not be the largest V-dd allowed by the given packaging platform, and that advanced cooling techniques can improve throughput significantly.
引用
收藏
页码:1042 / 1053
页数:12
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