Gate stack engineering to enhance high-κ/metal gate reliability for DRAM I/O applications

Continued scaling of DRAM technologies has required a limitation of the power dissipation from the peripheral region of the chip, while downscaling transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-kappa metal-gate (HKMG) stacks into periphery and high-voltage DRAM I/O devices. Being the peripheral region favours a gate first flow, which introduces significant reliability challenges, with the Negative Bias Temperature Instabilities (NBTI) in pMOS I/O devices severely degraded. We present and rationalise a dramatic improvement in NBTI robustness resulting from fluorine incorporation in the high-kappa layer or application of TaN electrodes. It is shown that these process sequences enable a reduction of bulk and interface defects which are present in the case of high-kappa/metal gate samples, thereby demonstrating performance comparable to the current polysilicon/SiO2 workhorse.