High Throughput and Fully Pipelined FPGA Implementation of AES-192 Algorithm

AES (Advanced Encryption Standard) is one of the most common and secured symmetric key cryptographic algorithms. AES has received considerable attention from scientists in latest years due to its broad spectrum of applications such as communication, military, network, electronic banking, Internet of Things (IoT), etc. AES can be implemented using software and hardware. Hardware implementation can be based on Field Programmable Gate Array (FPGA). By using hardware, a higher data rate for fast applications such as routers can be achieved compared to software implementation. In this paper we present an FPGA implementation for AES-192. We employ loop-unrolling, fully pipelining, and sub-pipelining techniques and other efficient methods for the most complex parts of AES-192 such as Mix-columns, S-boxes. Our AES-192 implementation using Xilinx Defense-Grade Virtex-7(XQ7VX330T-RF1157) FPGA achieves high throughput of 54.52 Gbps and maximum operational frequency of 425.996 MHZ.