On the prediction of geometry-dependent floating-body effect in SOI MOSFETs

被引:1
作者
Su, P [1 ]
Lee, W [1 ]
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
关键词
body source built-in potential lowering; floating-body effect; silicon-on-insulator (SOI) CMOS; threshold voltage; partially depleted (PD); fully depleted (FID);
D O I
10.1109/TED.2005.850626
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This brief demonstrates that, through the perspective of body-source built-in potential lowering (Delta V-bi), the geometry-dependent floating-body effect in state-of-the-art silicon-on-insulator (SOI) MOS-FETs can be explained and predicted by the geometry dependence of threshold voltage (V-T). The correlation between Delta V-bi and V-T unveiled in this brief is the underlying mechanism responsible for the coexistence of partially depleted and fully depleted devices in a single SOI chip.
引用
收藏
页码:1662 / 1664
页数:3
相关论文
共 18 条
[1]   THE INVERSE-NARROW-WIDTH EFFECT [J].
AKERS, LA .
IEEE ELECTRON DEVICE LETTERS, 1986, 7 (07) :419-421
[2]   A VLSI design methodology for SOI technology [J].
Allen, DH .
2004 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2004, :5-8
[3]  
[Anonymous], 2003, INT TECHNOLOGY ROADM
[4]  
BEARDEN D, P IEEE INT SOI C OCT, P6
[5]   A 45 nm gate length high performance SOI transistor for 100nm CMOS technology applications [J].
Celik, M ;
Krishnan, S ;
Fuselier, M ;
Wei, A ;
Wu, D ;
En, B ;
Cave, N ;
Abramowitz, P ;
Min, B ;
Pelella, M ;
Yeh, P ;
Burbach, G ;
Taylor, B ;
Jeon, Y ;
Qi, WJ ;
Li, RG ;
Conner, J ;
Yeap, G ;
Woo, M ;
Mendicino, M ;
Karlsson, O ;
Wristers, D .
2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, :166-167
[6]  
Cheng Y., 1999, MOSFET MODELING BSIM
[7]   THRESHOLD VOLTAGE MODEL FOR DEEP-SUBMICROMETER MOSFETS [J].
LIU, ZH ;
HU, CM ;
HUANG, JH ;
CHAN, TY ;
JENG, MC ;
KO, PK ;
CHENG, YC .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (01) :86-95
[8]   Application of an SOI 0.12-μm CMOS technology to SoCs with low-power and high-frequency circuits [J].
Plouchart, JO ;
Zamdmer, N ;
Kim, J ;
Sherony, M ;
Tan, Y ;
Ray, A ;
Talbi, M ;
Wagner, LF ;
Wu, K ;
Lustig, NE ;
Narasimha, S ;
O'Neil, P ;
Phan, N ;
Rohn, M ;
Strom, J ;
Friend, DM ;
Kosonocky, SV ;
Knebel, DR ;
Kim, S ;
Jenkins, KA ;
Rivier, MM .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2003, 47 (5-6) :611-629
[9]   DEEP-SUBMICROMETER CHANNEL DESIGN IN SILICON-ON-INSULATOR (SOI) MOSFETS (VOL 15, PG 183, 1994) [J].
SU, LT ;
JACOBS, JB ;
CHUNG, JE ;
ANTONIADIS, DA .
IEEE ELECTRON DEVICE LETTERS, 1994, 15 (09) :366-369
[10]   A unified model for partial-depletion and full-depletion SOI circuit designs: Using BSIMPD as a foundation [J].
Su, P ;
Fung, SKH ;
Wyatt, PW ;
Wan, H ;
Chan, MS ;
Niknejad, AM ;
Hu, CM .
PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, :241-244