A low-power wideband LNA exploiting current-reuse and noise cancelation techniques

This paper presents an inductorless low-power wideband Low Noise Amplifier (LNA) in TSMC 0.18 mu m CMOS technology. The proposed LNA is based on the Common-Gate (CG) topology, which consists of three consecutive stages: CG, Common-Source (CS), and Collector stage. The CG and CS configurations are responsible for providing the wideband input impedance matching and the majority of the gain, respectively. The overall performance of the LNA has been improved by applying noise cancelation, capacitive-peaking, and current reuse techniques. Unlike the conventional structure, the CG and CS sections' noise is canceled by utilizing a novel noise-canceling mechanism, simultaneously. Furthermore, with the capacitive-peaking technique, the voltage gain drop across hi gher frequencies is prevented, and thus, the bandwidth of the structure is improved. The trade-off between power consumption and input impedance has been dramatically resolved by employing the current reuse technique in the CG stage. Post-layout simulation results of the presented noise-canceling LNA demonstrate a Noise Figure (NF) of 2.19-2.58 dB and a maximum voltage gain of 19.84 dB with a -3 dB bandwidth of 0.2-2.85 GHz. The simulated input/output matching (i.e., S11/S22) is better than -14.73/-19.43 dB in the entire bandwidth. Additionally, Input Third Intercept Point (IIP3) of -4.56 dBm is achieved. The results are gained by consuming only 2.87 mW under a supply voltage of 1.2 V and occupying a 0.0429 mm(2) of die area.