An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration

被引：21

作者：

Radulescu, A ^{[1
]}

Dielissen, J ^{[1
]}

Goossens, K ^{[1
]}

Rijpkerna, E ^{[1
]}

Wielage, P ^{[1
]}

机构：

[1] Philips Res Labs, Eindhoven, Netherlands

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/DATE.2004.1268998

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL. Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143 mm(2) in a 0.13 mum technology, and runs at 500 MHz.

引用

页码：878 / 883

页数：6