Monolayer Graphene Field Effect Transistor-Based Operational Amplifier

被引：9

作者：

Safari, Ali ^{[1
]}

Dousti, Massoud ^{[2
]}

Tavakoli, Mohammad Bagher ^{[1
]}

机构：

[1] Islamic Azad Univ, Dept Elect Engn, Arak Branch, Arak, Iran

[2] Islamic Azad Univ, Dept Elect & Comp Engn, Sci & Res Branch, Tehran, Iran

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2019年 / 28卷 / 03期

关键词：

Monolayer graphene field effect Transistor (mGFET); Op-Amp; Verilog-A; ADS; Silvaco; COMPACT MODEL;

D O I：

10.1142/S021812661950052X

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Graphene Field Effect Transistor (GFET) is a promising candidate for future high performance applications in the beyond CMOS roadmap for analog circuit applications. This paper presents a Verilog-A implementation of a monolayer graphene field-effect transistor (mGFET) model. The study of characteristic curves is carried out using advanced design system (ADS) tools. Validation of the model through comparison with measurements from the characteristic curves is carried out using Silvaco TCAD tools. Finally, the mGFET is used to design a GFET-based operational amplifier (Op-Amp). The GFET Op-Amp performances are timed in term of the graphene channel length in order to obtain a reasonable gain and bandwidth. The main characteristics of the Op-Amp performance are compared with 0.18 mu m CMOS technology.

引用

页数：14

共 50 条

[41] Design, Simulation and Comparative Analysis of Two Stage Operational Amplifier Based on CNTFETs Using Indirect Feedback Frequency Compensation [J].

Islam, Mir Bintul ;

Nizamuddin, M. ;

Islam, S. S. .

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2024, 33 (09)

[42] Modeling and Simulation of Ion-Sensitive Field-Effect Transistor using TCAD Methodology [J].

Choksi, Neel ;

Sewake, Dewanshu ;

Sinha, Soumendu ;

Mukhiya, Ravindra ;

Sharma, Rishi .

2017 1ST INTERNATIONAL CONFERENCE ON ELECTRONICS, MATERIALS ENGINEERING & NANO-TECHNOLOGY (IEMENTECH), 2017,

[43] High-gain, high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower [J].

Centurelli, Francesco ;

Monsurro, Pietro ;

Trifiletti, Alessandro .

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2019, 47 (04) :499-512

[44] Improved Simple DC Model of Vertical-Slit Field-Effect Transistor (VeSFET) [J].

Pfitzner, Andrzej .

2014 PROCEEDINGS OF THE 21ST INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS & SYSTEMS (MIXDES), 2014, :323-327

[45] Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor [J].

Yadav, Snehlata ;

Rewari, Sonam ;

Pandey, Rajeshwari .

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 2024, 37 (02)

[46] Large-Signal Model of Graphene Field-Effect Transistors-Part II: Circuit Performance Benchmarking [J].

Pasadas, Francisco ;

Jimenez, David .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (07) :2942-2947

[47] Intrinsic rectification in common-gated graphene field-effect transistors [J].

Haddad, Pierre-Antoine ;

Flandre, Denis ;

Raskin, Jean-Pierre .

NANO ENERGY, 2018, 43 :37-46

[48] Comparison of simulation models for the coaxially-gated carbon-nanotube field-effect transistor [J].

Jong-Myeon Park ;

Jae-Hong An ;

Shin-Nam Hong .

Journal of the Korean Physical Society, 2012, 61 :410-414

[49] The drain velocity overshoot in an 80 nm metal-oxide-semiconductor field-effect transistor [J].

Tan, Michael L. P. ;

Arora, Vijay K. ;

Saad, Ismail ;

Ahmadi, Mohammad Taghi ;

Ismail, Razali .

JOURNAL OF APPLIED PHYSICS, 2009, 105 (07)

[50] Progress on a Carbon Nanotube Field-Effect Transistor Integrated Circuit: State of the Art, Challenges, and Evolution [J].

Chen, Zhifeng ;

Chen, Jiming ;

Liao, Wenli ;

Zhao, Yuan ;

Jiang, Jianhua ;

Chen, Chengying .

MICROMACHINES, 2024, 15 (07)

← 1 2 3 4 5 →