Performance model for inter-chip communication considering inductive cross-talk and cost

被引：0
|
作者：
LaMeres, BJ [1 ]
Khatri, SP [1 ]
机构：
[1] Univ Colorado, Dept Elect & Comp Engn, Boulder, CO 80309 USA
来源：
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年
关键词：
D O I：
10.1109/ISCAS.2005.1465540
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present an analytical method to perform the design of the I/O subsystem of an IC given its throughput requirements. Our method can be used to select the IC package, along with the bus size and speed so as to minimize I/O cost. We have validated our model by conducting simulations on three industry-standard packages while varying the bus width, slew rate, and signal-to-power ground ratio. Our experimental results track closly with the analytical model. We demonstrate for the package considered that it is more cost effective to use faster, narrower busses rather than slower wider busses to achieve a desired system throughput.
引用
收藏
页码：4130 / 4133
页数：4
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