Limits to binary logic switch scaling - A Gedanken model

被引：311

作者：

Zhirnov, VV ^{[1
]}

Cavin, RK

Hutchby, JA

Bourianoff, GI

机构：

[1] Semicond Res Corp, Res Triangle Pk, NC 27709 USA

[2] Intel Corp, Austin, TX 78746 USA

来源：

PROCEEDINGS OF THE IEEE | 2003年 / 91卷 / 11期

关键词：

closely pocked devices; device scaling limits; digital integrated circuits; heat removal; nanotechnology; power consumption; tunneling;

D O I：

10.1109/JPROC.2003.818324

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we consider device scaling and speed limitations on irreversible von Neumann computing,that arc derived from the requirement of "least energy computation." We consider computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state.

引用

页码：1934 / 1939

页数：6

共 12 条

[1]

BATE RT, 1982, VLSI ELECT, V5

[2]

FRENCH AP, 1978, INTRO QUANTUM PHYSIC

[3] FUNDAMENTAL LIMITS IN DIGITAL INFORMATION-PROCESSING [J].