Scaling Solder Micro-Bump Interconnect Down to 10 μm Pitch for Advanced 3D IC Packages

被引：24

作者：

Li, Zhaozhi ^{[1
]}

Tomita, Yoshihiro ^{[1
]}

Elsherbini, Adel A. ^{[2
]}

Liu, Pilin ^{[3
]}

Sawyer, Holly A. ^{[4
]}

Swan, Johanna M. ^{[2
]}

Liff, Shawna M. ^{[1
]}

机构：

[1] Intel Corp, Assembly & Test Technol Dev, Chandler, AZ 85226 USA

[2] Intel Corp, Components Res, Chandler, AZ 85226 USA

[3] Intel Corp, Corp Qual Network, Chandler, AZ 85226 USA

[4] Intel Corp, Fab Sort Mfg, Hillsboro, OR USA

来源：

IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021) | 2021年

关键词：

Pitch scaling; micro-bump interconnect; diffusion barrier; intermetallic compound; thermo-compression bonding; die to die 3D stacking; electromigration; isothermal aging;

D O I：

10.1109/ECTC32696.2021.00082

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses the efforts to shrink the micro-bump pitch to 20 mu m and then 10 mu m with solder micro-bumps for silicon-on-silicon 3D assembly by leveraging alternate solder diffusion barrier metals and tuning the assembly process to realize both good yield and reliable interconnects. Specifically in this paper, the assembly process challenges arc detailed and the impact of our barrier metal assessment and process optimization to resolve these technical challenges are discussed through the study of solder joint reliability results using internal 20 mu m pitch and 10 mu m pitch solder micro-bump test-vehicles (TV).

引用

页码：451 / 456

页数：6

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