0.1 mu m MOSFET with super self-aligned shallow junction electrodes

被引:0
|
作者
Ishii, M [1 ]
Goto, K [1 ]
Sakuraba, M [1 ]
Matsuura, T [1 ]
Murota, J [1 ]
Kudoh, Y [1 ]
Koyanagi, M [1 ]
机构
[1] TOHOKU UNIV,ELECT COMMUN RES INST,LAB ELECT INTELLIGENT SYST,AOBA KU,SENDAI,MIYAGI 98077,JAPAN
来源
ULSI SCIENCE AND TECHNOLOGY / 1997: PROCEEDINGS OF THE SIXTH INTERNATIONAL SYMPOSIUM ON ULTRALARGE SCALE INTEGRATION SCIENCE AND TECHNOLOGY | 1997年 / 1997卷 / 03期
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Super Self-aligned Shallow junction Electrode MOSFET's((SEMOSFET)-E-3) with a 0.1 mu m gate length are fabricated by utilizing in-situ impurity doped selective epitaxy on the source/drain regions at 550 degrees C by Si1-xGex CVD. Normal saturation characteristics were observed and drastic improvements of the current drivability were performed by annealing and selective tungsten growth. Threshold voltage scarcely showed a shift with the gate length, which means that the short channel effect is greatly suppressed in (SE)-E-3-MOSFET. The results show very high potentials for an ultrasmall MOSFET, because the effective channel length is almost the same as the fabricated gate length and the source/drain junctions are extremely shallow.
引用
收藏
页码:441 / 449
页数:9
相关论文
共 50 条
  • [21] SELF-ALIGNED ELECTRODES TO UNDERLYING IMPLANTED REGIONS.
    Koburger, C.W.
    White, F.R.
    IBM technical disclosure bulletin, 1983, 26 (7 A): : 3108 - 3109
  • [22] A NEW VERTICAL DOUBLE DIFFUSED MOSFET - THE SELF-ALIGNED TERRACED-GATE MOSFET
    UEDA, D
    TAKAGI, H
    KANO, G
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (04) : 416 - 420
  • [23] Self-aligned electrodes for suspended carbon nanotube structures
    Robinson, LAW
    Lee, SB
    Teo, KBK
    Chhowalla, M
    Amaratunga, GAJ
    Milne, WI
    Williams, DA
    Hasko, DG
    Ahmed, H
    MICROELECTRONIC ENGINEERING, 2003, 67-8 : 615 - 622
  • [24] An advanced non-classical self-aligned quasi-SOI MOSFET with Π-shaped semiconductor conductive layer to ease ultra-shallow junction requirement
    Lin, Jyi-Tsong
    Eng, Yi-Chuen
    Tsai, Ying-Chieh
    Tseng, Hung-Jen
    Tseng, Yi-Ming
    Lin, Po-Hsieh
    Kang, Shiang-Shi
    Lin, Jeng-Da
    Huang, Hau-Yuan
    Kao, Kung-Kai
    EXTENDED ABSTRACTS 2008 INTERNATIONAL WORKSHOP ON JUNCTION TECHNOLOGY, 2008, : 187 - 190
  • [25] A 0.4 mu m(2) self-aligned AND-type flash memory cell technology
    Adachi, T
    Kato, M
    Kobayashi, T
    Sudo, Y
    Kume, H
    Morimoto, T
    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS, 1997, 80 (04): : 85 - 91
  • [26] DOPANT REDISTRIBUTION EFFECT ON POST-JUNCTION SILICIDE SCHEME SHALLOW JUNCTION AND A PROPOSAL OF NOVEL SELF-ALIGNED SILICIDE SCHEME
    OHTOMO, A
    IDA, J
    YONEKAWA, K
    KAI, K
    AIKAWA, I
    KITA, A
    NISHI, K
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1994, 33 (1B): : 475 - 479
  • [27] 1.25-MU-M DEEP-GROOVE-ISOLATED SELF-ALIGNED ECL CIRCUITS
    TANG, DD
    SOLOMON, PM
    NING, TH
    ISAAC, RD
    BURGER, RE
    ISSCC DIGEST OF TECHNICAL PAPERS, 1982, 25 : 242 - 243
  • [28] 1.25 MU-M DEEP-GROOVE-ISOLATED SELF-ALIGNED BIPOLAR CIRCUITS
    TANG, DD
    SOLOMON, PM
    NING, TH
    ISAAC, RD
    BURGER, RE
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (05) : 925 - 931
  • [30] A METAL-GATE SELF-ALIGNED MOSFET USING NITRIDE OXIDE
    SCHMIDT, MA
    RAFFEL, JI
    TERRY, FL
    SENTURIA, SD
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (03) : 643 - 648