A Design of 5.8GHz Tunable Band Noise Cancelling CMOS LNA for DSRC Communications

被引：2

作者：

Lee, Dong Won ^{[1
]}

Lee, Kang-Yoon ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Dept Elect & Comp Engn, Suwon, South Korea

来源：

2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020) | 2020年

关键词：

DSRC; Noise Cancelling; Active Balun;

D O I：

10.1109/ISOCC50952.2020.9332934

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This article presents about 5.8GHz noise cancelling CMOS LNA for DSRC communication. The LNA is designed with differential output with balun architecture and resistive-feedback noise cancelling technique. Tunable load capacitor bank achieves wideband input matching and gain selection. The LNA is implemented in 130nm CMOS technology and achieves a simulated gain of 24.2dB and P1dB of -13.46dB and noise figure(NF) of 2.74dB at center frequency. The power consumption is 10.51mW at 1.2V power supply. The chip area is 509X559 mu m2

引用

页码：89 / 90

页数：2