Bit-serial multiplication in GF(2m) using irreducible all-one polynomials

被引：31

作者：

Fenn, STJ ^{[1
]}

Parker, MG

Benaissa, M

Taylor, D

机构：

[1] Univ Huddersfield, Dept Elect & Elect Engn, Huddersfield HD1 3DH, W Yorkshire, England

[2] Univ Bradford, Dept Elect & Elect Engn, Bradford BD7 1DP, W Yorkshire, England

来源：

IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES | 1997年 / 144卷 / 06期

关键词：

bit-serial multipliers; Reed-Solomon codes; VLSI; cryptography;

D O I：

10.1049/ip-cdt:19971586

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Two architectures for carrying out bit-serial multiplication in GF(2(m)) are presented where the defining irreducible polynomial for the field is an all-one polynomial. The multipliers presented have low hardware requirements, regular structures and are therefore suitable for VLSI implementation.

引用

页码：391 / 393

页数：3

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