A PVT Resistant Coarse-fine Time-to-Digital Converter

被引：0
|
作者：
Jedari, Esrafil [1 ]
Rashidzadeh, Rashid [1 ]
Saif, Mehrdad [1 ]
机构：
[1] Univ Windsor, Dept Elect & Comp Engn, Windsor, ON, Canada
来源：
2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2017年
基金：
加拿大自然科学与工程研究理事会;
关键词：
PVT resistant; high-resolution time interval measurement; time-to-digital converter (TDC); Vernier TDC; CMOS; DELAY;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a fine-coarse time interval measurement scheme which is resilient to the variations of process, voltage, and temperature (PVT). Two Delay Locked Loops (DLLs) have been utilized to minimize the effects of PVT on the measured time intervals. A two-step time-to-digital converter is designed to ensure a high-resolution measurement over a wide dynamic range. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using ADS tools indicate that the measurement resolution varies by less than 0.12ps with +/- 15% variations of power supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement resolution changes by few femtoseconds from slow to fast corners for process variations and it varies by a maximum of 0.1ps with changes from -40 degrees C to + 100 degrees C in temperature.
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页数：4
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