Single-Inductor Multioutput-Level Buck Converter for Reducing Voltage-Transition Time and Energy Overheads in Low Power DVS-Enabled Systems

Dynamic voltage scaling (DVS) is a useful technique to optimize performance and efficiency of CMOS digital processors using dc-dc converters that require to meet extremely fast slew rate demand. However, there exist conflicting design criteria in existing DVS power supply architectures. This paper proposes a single-inductor multioutput-level buck converter for low power DVS-enabled systems. Under the time optimal voltage transition recovery, the proposed architecture: first, achieves the performance much beyond system's physical limits compared to conventional synchronous and multiphase buck converter based architectures; and second, can overcome conflicting power circuit design criteria in existing architectures. Also, a high-resolution quantized voltage can be realized by using a voltage-dithering technique. An analytical framework is considered to formulate various processor and converter-induced energy overheads. A comparative study is shown to evaluate the usefulness of the proposed architecture over the existing approaches under frequent voltage transitions. A prototype single-inductor four-output-level buck converter is tested and the performance improvements are demonstrated using test results.