Optimisation of on-chip design-for-test infrastructure for maximal multi-site test throughput

Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. The authors pro\pose a test flow with large multi-site testing during wafer test, enabled by a narrow SOC-ATE test interface, and relatively small multi-site testing during final (packaged-IC) test, in which all SOC pins need to be contacted. They present a throughput model for multi-site testing, valid for both wafer test and final test, which considers the effects of test time, index time, abort-on-fail and re-test after contact fails. Conventional multi-site testing requires sufficient ATE channels to allow testing of multiple SOCs in parallel. Instead, a given fixed ATE is assumed, and for a given SOC they design and optimise the on-chip design-for-test infrastructure, in order to maximise the throughput during wafer test. The on-chip DfT consists of an E-RPCT wrapper, and, for modularly tested SOCs, module wrappers and TAMs. Subsequently, for the designed test infrastructure, they also maximise the test throughput for final test by tuning its multi-site number. Finally, they present experimental results for the ITC'02 SOC Test Benchmarks and a complex Philips SOC.