Double-gate 1T-DRAM cell using nonvolatile memory function for improved performance

被引：6

作者：

Park, Ki-Heung ^{[3
,4
]}

Cristoloveanu, Sorin ^{[4
]}

Bawedin, Maryline ^{[4
]}

Bae, Youngho ^{[4
,5
]}

Na, Kyoung-Il ^{[4
]}

Lee, Jong-Ho ^{[1
,2
]}

机构：

[1] Seoul Natl Univ, Sch EECS Eng, Seoul 151600, South Korea

[2] Seoul Natl Univ, ISRC, Interuniv Res Ctr, Seoul 151600, South Korea

[3] Samsung Elect Co Ltd, Foundry Business Team, Yongin 446711, Kyunggi Do, South Korea

[4] MINATEC, Grenoble Polytech Inst, IMEP, LAHC,UMR 5130, F-38016 Grenoble 1, France

[5] Uiduk Univ, Dept Elect Engn, Gyeongju 780713, South Korea

来源：

SOLID-STATE ELECTRONICS | 2011年 / 59卷 / 01期

关键词：

1T-DRAM; DRAM; Double-gate (DG) MOSFET; Nonvolatile memory; Floating-body effect; Silicon-on-insulator (SOI); MOSFETs;

D O I：

10.1016/j.sse.2011.01.007

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a double-gate (DG) 1T-DRAM cell combining SONOS type storage node on the back-gate (control-gate) for nonvolatile memory function. The cell sensing margin and retention time characteristics were systematically examined in terms of control-gate voltage (V(cg)) and nonvolatile memory (NVM) function. The additional NVM function is achieved by Fowler-Nordheim (FN) tunneling electron injection into the nitride storage node. The injected electrons induce a permanent hole accumulation layer in silicon body which improves the sensing margin and retention time characteristics. To demonstrate the effect of stored electrons in the nitride layer, experimental data are provided using 0.6 mu m devices fabricated on SOI wafers. (C) 2011 Elsevier Ltd. All rights reserved.

引用

页码：39 / 43

页数：5