Low Inductance PCB Layout for GaN Devices: Interleaving Scheme

Wide-Bandgap devices are pushing the boundaries of switching frequencies, power densities, and efficiencies of modern power converters. To utilize the full potential of these devices, the parasitic elements formed by the printed circuit board (PCB) layout requires special attention. This work introduces a novel approach, that helps to reduce the parasitic inductance of the commutation loop in a half-bridge topology with surface-mount power devices. The approach uses multiple PCB layers for enhanced current distribution and magnetic cancellation, which results in low inductance designs with less sensitivity to the geometric parameters of the PCB design. The approach is validated with simulation results via a Finite Element Analysis (FEA) as well as with experiments. The results show a promising reduction in inductance and geometric sensitivity compared to the conventional solution.