Design of New Logic Architectures Utilizing Optimized Suspended-Gate Single-Electron Transistors

被引：1
|
作者：
Pruvost, Benjamin [1 ]
Uchida, Ken [1 ,2 ,3 ]
Mizuta, Hiroshi [2 ,3 ]
Oda, Shunri [1 ,2 ,3 ]
机构：
[1] Tokyo Inst Technol, Quantum Nanoelect Res Ctr, Tokyo 1528552, Japan
[2] Tokyo Inst Technol, Dept Phys Elect, Tokyo 1528552, Japan
[3] Japan Sci & Technol, Solut Oriented Res Sci & Technol, Tsukuba, Ibaraki 3058501, Japan
来源：
IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2010年 / 9卷 / 04期
关键词：
1-D and 3-D modeling; cantilever switch; movable gate; nanoelectromechanical system (NEMS); single-electron transistor (SET);
D O I：
10.1109/TNANO.2009.2030502
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The operation and performances of the suspended-gate single-electron transistor (SET) are investigated through simulation. The movable gate is 3-D optimized, so that low actuation voltage (0.4 V), fast switching (1 ns), and ultralow pull-in energy (0.015 fJ) are simulated. A two-state capacitor model based on the 3-D results is then embedded with a SET analytical model in a SPICE environment to investigate the operation of the device. Through the control of the Coulomb oscillation characteristics, the position of the movable gate enables a background charge insensitive coding of the information. New circuit architectures with applications in cellular nonlinear network and pattern matching are also proposed and simulated.
引用
收藏
页码：504 / 512
页数：9
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