Multiple-chip module design optimizations using a novel layout parameterization technique

被引：1
作者：
Huang, CWP [1 ]
Dow, GS [1 ]
Bao, JW [1 ]
Kuran, S [1 ]
Sercu, J [1 ]
机构：
[1] ANADIGICS Inc, Warren, NJ 07059 USA
来源：
2003 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS | 2003年
关键词：
D O I：
10.1109/RFIC.2003.1214015
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel layout parameterization technique for multi-chip module design optimizations is presented. This technique is based on a quasi-static method of moments and multi-dimensional interpolation, which can reduce a 12-minute electromagnetic layout simulation to 5.3 seconds. Excellent CDMA power amplifier (PA) module performance is achieved based on this technique.
引用
收藏
页码：587 / 590
页数：4
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