Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs

被引：25

作者：

Ghanatian, Hamdam ^{[1
]}

Hosseini, Seyed Ebrahim ^{[1
]}

机构：

[1] Ferdowsi Univ Mashhad, Dept Elect Engn, Mashhad, Iran

来源：

JOURNAL OF COMPUTATIONAL ELECTRONICS | 2016年 / 15卷 / 02期

关键词：

Analytical model; Trigate SOI MOSFET; 3-D Poisson's equation; Parabolic potential distribution; Subthreshold swing; Conduction path; Mobile charges; GATE; SI;

D O I：

10.1007/s10825-016-0817-2

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new analytical model for the subthreshold swing of nanoscale undoped trigate silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed, based on the channel potential distribution and physical conduction path concept. An analytical model for the potential distribution is obtained by solving the three-dimensional (3-D) Poisson's equation, assuming a parabolic potential distribution between the lateral gates. In addition, mobile charges are considered in the model. The proposed analytical model is investigated and compared with results obtained from 3-D simulations using the ATLAS device simulator and experimental data. It is demonstrated that the analytical model predicts the subthreshold swing with good accuracy for different lengthes, thicknesses, and widths of channel.

引用

页码：508 / 515

页数：8

共 30 条

[1] A two-dimensional model for interface coupling in triple-gate transistors [J].

Akarvardar, Kerem ;

Mercha, Abdelkarim ;

Cristoloveanu, Sorin ;

Gentil, Pierre ;

Simoen, Eddy ;

Subramanian, Vaidy ;

Claeys, Cor .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (04) :767-775

[2]

[Anonymous], 2008, ATL US MAN DEV SIM S

[3]

Cartwright J., Nature News, DOI DOI 10.1038/NEWS.2011.274

[4]

Colinge JP, 2008, INTEGR CIRCUIT SYST, P1, DOI 10.1007/978-0-387-71752-4_1

[5] Multiple-gate SOI MOSFETs [J].

Colinge, JP .

SOLID-STATE ELECTRONICS, 2004, 48 (06) :897-905

[6] Multi-gate devices for the 32nm technology node and beyond [J].

Collaert, N. ;

De Keersgieter, A. ;

Dixit, A. ;

Ferain, I. ;

Lai, L. -S. ;

Lenoble, D. ;

Mercha, A. ;

Nackaerts, A. ;

Pawlak, B. J. ;

Rooyackers, R. ;

Schulz, T. ;

San, K. T. ;

Son, N. J. ;

Van Dald, M. J. H. ;

Verheyen, P. ;

von Amim, K. ;

Witters, L. ;

De Meyer, K. ;

Biesemans, S. ;

Jurczak, M. .

ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, :143-+

[7]

Cristoloveanu S., 2004, International Journal of High Speed Computing, V14, P465, DOI 10.1142/S0129156404002466

[8]

Doyle B., 2002, Intel Technology Journal, V6, P42

[9] A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part I: Charge Model [J].

Duarte, Juan Pablo ;

Choi, Sung-Jin ;

Moon, Dong-Il ;

Ahn, Jae-Hyuk ;

Kim, Jee-Yeon ;

Kim, Sungho ;

Choi, Yang-Kyu .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (02) :840-847

[10] A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part II: Drain Current Model [J].