Gate oxide integrity for polysilicon thin-film transistors: A comparative study for ELC, MILC, and SPC crystallized active polysilicon layer

被引：0

作者：

Choi, DC ^{[1
]}

Choi, BD ^{[1
]}

Jung, JY ^{[1
]}

Park, HH ^{[1
]}

Seo, JW ^{[1
]}

Lee, KY ^{[1
]}

Chung, HK ^{[1
]}

机构：

[1] Samsung SDI, Adv Technol Inst, Yongin 442391, Kyoungki, South Korea

来源：

Amorphous and Nanocrystalline Silicon Science and Technology-2005 | 2005年 / 862卷

关键词：

D O I：

暂无

中图分类号：

O7 [晶体学];

学科分类号：

0702 ; 070205 ; 0703 ; 080501 ;

摘要：

In this paper, we present the results of Plasma Enhanced Chemical Vapor Deposition gate oxide (SiO2) integrity on ELC (excimer laser crystallized), MILC (metal induced lateral crystallized) and SPC (solid phase crystallized) polysilicon films. We observed that gate oxide strength of poly Si TFT strongly depends on the crystallization method for the active silicon layer. In the case of ELC films, asperities on the silicon surface reduce the SiO2 breakdown field significantly. The metallic contaminants in MILC films are responsible for a deleterious impact on gate oxide integrity. Among the three cases, the SiO2 breakdown field was the highest for the SPC silicon films. The breakdown fields at the 50% failure points in Weibull plots for the ELC, MILC and SPC cases were 5.1MV/cm, 6.2MV/cm, 8.1MV/cm, respectively. We conclude that the roughness and metallic contamination of the poly Si films are the main factors that cause enhanced breakdown of SiO2 films.

引用

页码：647 / 651

页数：5

共 50 条

[41] Performance enhancement of offset gated polysilicon thin-film transistors
Dimitriadis, CA
Miyasaka, M
IEEE ELECTRON DEVICE LETTERS, 2000, 21 (12) : 584 - 586
[42] Effects of DC gate and drain bias stresses on the degradation of excimer laser crystallized polysilicon thin film transistors
Kouvatsos, DN
Michalas, L
Voutsas, AT
Papaioannou, GJ
Second Conference on Microelectronics, Microsystems and Nanotechnology, 2005, 10 : 45 - 48
[43] Gate bias stress in hydrogenated and unhydrogenated polysilicon thin film transistors
LUSAC, Octeville, France
Microelectronics Reliability, 1998, 38 (6-8): : 1149 - 1153
[44] Gate bias stress in hydrogenated and unhydrogenated polysilicon thin film transistors
Tala-Ighil, B
Toutah, H
Rahal, A
Mourgues, K
Pichon, L
Raoult, F
Bonnaud, O
Mohammed-Brahim, T
MICROELECTRONICS AND RELIABILITY, 1998, 38 (6-8): : 1149 - 1153
[45] A STUDY OF HYDROGEN PASSIVATION OF GRAIN-BOUNDARIES IN POLYSILICON THIN-FILM TRANSISTORS
FAUGHNAN, B
IPRI, AC
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (01) : 101 - 107
[46] HIGH-MOBILITY BOTTOM-GATE THIN-FILM TRANSISTORS WITH LASER-CRYSTALLIZED AND HYDROGEN-RADICAL-ANNEALED POLYSILICON FILMS
SHIMIZU, K
HOSOYA, H
SUGIURA, O
MATSUMURA, M
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 1991, 30 (12B): : 3704 - 3709
[47] Reverse short-channel effect in metal-induced laterally crystallized polysilicon thin-film transistors
Wong, M
Bhat, GA
Kwok, HS
IEEE ELECTRON DEVICE LETTERS, 1999, 20 (11) : 566 - 568
[48] Effects of Channel Width and Nitride Passivation Layer on Electrical Characteristics of Polysilicon Thin-Film Transistors
Liao, Chia-Chun
Lin, Min-Chen
Chiang, Tsung-Yu
Chao, Tien-Sheng
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (11) : 3812 - 3819
[49] Electrical stressing effects in solid-phase crystallized polysilicon thin film transistors
Kouvatsos, DN
Vamvakas, VE
Davazoglou, D
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2002, 17 (06) : 515 - 521
[50] Modeling of I-V characteristics in symmetric double-gate polysilicon thin-film transistors
Ma, Xiaoyu
Chen, Songlin
Deng, Wanling
Huang, Junkai
AIP ADVANCES, 2017, 7 (06):

← 1 2 3 4 5 →