An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and VMIN Optimization

被引：19

作者：

Meinerzhagen, Pascal A. ^{[1
]}

Tokunaga, Carlos ^{[1
]}

Malavasi, Andres ^{[1
]}

Vaidya, Vaibhav ^{[1
]}

Mendon, Ashwin ^{[1
]}

Mathaikutty, D. ^{[1
]}

Kulkarni, Jaydeep ^{[1
]}

Augustine, Charles ^{[1
]}

Cho, Minki ^{[1
]}

Kim, Stephen T. ^{[1
]}

Matthew, George E. ^{[1
]}

Jain, Rinkle ^{[1
]}

Ryan, Joseph ^{[1
]}

Peng, Chung-Ching ^{[1
]}

Paul, Somnath ^{[1
]}

Vangal, Sriram ^{[1
]}

Esparza, Brando Perez ^{[1
]}

Cuellar, L. ^{[1
]}

Woodman, M. ^{[1
]}

Iyer, Bala ^{[1
]}

Maiyuran, Subramaniam ^{[1
]}

Chinya, G. ^{[1
]}

Zou, Xiang ^{[1
]}

Liao, Yuyun ^{[1
]}

Ravichandran, Krishnan ^{[1
]}

Wang, H. ^{[1
]}

Khellah, Muhammad M. ^{[1
]}

Tschanz, James W. ^{[1
]}

De, Vivek ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2019年 / 54卷 / 01期

关键词：

Energy-efficient graphics processing unit (GPU); fine-grain dynamic voltage and frequency scaling (DVFS); integrated voltage regulators (IVRs); retentive sleep; V-MIN optimization;

D O I：

10.1109/JSSC.2018.2875097

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Graphics workloads make highly dynamic use of resources such as execution units (EUs), and thus can benefit from fast, fine-grain dynamic voltage and frequency scaling (DVFS) and retentive sleep. This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an integrated voltage regulator (IVR). The IVR enables energy-efficient EU turbo operation, data retention, and V-MIN optimization per EU. Silicon measurements show that IVR-enabled EU turbo operation offers up to 32% (average 29%) energy reduction at constant performance.

引用

页码：144 / 157

页数：14

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