A 0.18μm, 1.8-V CMOS high gain fully differential opamp utilized in pipelined ADC

A fully differential, high gain opamp to be used in a low-voltage low-power high speed pipeline analog to digital converter (ADC) in a 0.18 mu m CMOS process is designed. The opamp architecture is based on folded cascode and "double differential amplifier" technique. This design operates of a 1.8V power supply, achieving a differential output swing of +/- 1.65V, a DC gain of > 95 dB with a unity gain at 312MHz and a phase margin of 560 anti 0.5mW power dissipation. The operational transconductance amplifier (OTA) can be used to design high-speed ADCs, for local wireless communications. The minimized power dissipation opamp could be used in high resolution, high speed pipelined analog to digital converters, which are needed in applications requiring both high data rate and high speed, such as wireless LANs.