Mutation-based Compliance Testing for RISC-V

被引:1
|
作者
Herdt, Vladimir [1 ,2 ]
Tempel, Soren [1 ]
Grosse, Daniel [2 ,3 ]
Drechsler, Rolf [1 ,2 ]
机构
[1] Univ Bremen, Inst Comp Sci, Bremen, Germany
[2] DFKI GmbH, Cyber Phys Syst, Bremen, Germany
[3] Johannes Kepler Univ Linz, Inst Complex Syst, Linz, Austria
关键词
RISC-V; Compliance Testing; Mutation; Instruction Set Simulation; Symbolic Execution; GENERATION;
D O I
10.1145/3394885.3431584
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Compliance testing for RISC-V is very important. Essentially, it ensures that compatibility is maintained between RISC-V implementations and the ever growing RISC-V ecosystem. Therefore, an official Compliance Test-suite (CT) is being actively developed. However, it is very difficult to achieve that all relevant functional behavior is comprehensively tested. In this paper, we propose a mutation-based approach to boost RISC-V compliance testing by providing more comprehensive testing results. Therefore, we define mutation classes tailored for RISC-V to assess the quality of the CT and provide a symbolic execution framework to generate new test-cases that kill the undetected mutants. Our experimental results demonstrate the effectiveness of our approach. We identified several serious gaps in the CT and generated new tests to close these gaps.
引用
收藏
页码:55 / 60
页数:6
相关论文
共 50 条
  • [21] RISC-VTF: RISC-V Based Extended Instruction Set for Transformer
    Jiao, Qiang
    Hu, Wei
    Liu, Fang
    Dong, Yong
    2021 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS (SMC), 2021, : 1565 - 1570
  • [22] A Security Architecture for RISC-V based IoT Devices
    Auer, Lukas
    Skubich, Christian
    Hiller, Matthias
    2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2019, : 1154 - 1159
  • [23] An Automated Compiler for RISC-V Based DNN Accelerator
    Wu, Zheng
    Xie, Wuzhen
    Yi, Xiaoling
    Yang, Haitao
    Pu, Ruiyao
    Xiong, Xiankui
    Yao, Haidong
    Chen, Chixiao
    Tao, Jun
    Yang, Fan
    2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, : 3097 - 3101
  • [24] Randomized Testing of RISC-V CPUs Using Direct Instruction Injection
    Joannou, Alexandre
    Rugg, Peter
    Woodruff, Jonathan
    Fuchs, Franz A.
    van der Maas, Marno
    Naylor, Matthew
    Roe, Michael
    Watson, Robert N. M.
    Neumann, Peter G.
    Moore, Simon W.
    IEEE DESIGN & TEST, 2024, 41 (01) : 40 - 49
  • [25] Rapid RISC: Fast Customization of RISC-V Processors
    Donofrio, David D.
    Leidel, John D.
    OPEN ARCHITECTURE/OPEN BUSINESS MODEL NET-CENTRIC SYSTEMS AND DEFENSE TRANSFORMATION 2022, 2022, 12119
  • [26] An Optimized Implementation of Activation Instruction Based on RISC-V
    Yu, Hongjiang
    Yuan, Guoshun
    Kong, Dewei
    Chen, Chuhuai
    ELECTRONICS, 2023, 12 (09)
  • [27] Neutron Radiation Testing of RISC-V TMR Soft Processors on SRAM-Based FPGAs
    Wilson, Andrew E.
    Wirthlin, Michael
    Baker, Nathan G.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2023, 70 (04) : 603 - 610
  • [28] A Mutation-Based Approach for Testing AsmetaL Specifications
    Jameleddine Hassine
    Osama Alkrarha
    Arabian Journal for Science and Engineering, 2015, 40 : 3523 - 3544
  • [29] RISC-V Dives Into AI > Demand for machine learning means RISC-V chips will be everywhere
    Moore, Samuel K.
    IEEE SPECTRUM, 2022, 59 (04) : 5 - 7
  • [30] RISC-V2: A Scalable RISC-V Vector Processor
    Patsidis, Kariofyllis
    Nicopoulos, Chrysostomos
    Sirakoulis, Georgios Ch
    Dimitrakopoulos, Giorgos
    2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,