CNN inference simulator for accurate and efficient accelerator design

被引：0
|
作者：
Choi, Seong Bin [1 ]
Lee, Sang Seol [1 ]
Jang, Sung Joon [1 ]
机构：
[1] Korea Elect Technol Inst, Intelligent Image Proc Res Ctr, Seongnam, South Korea
来源：
2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2019年
关键词：
convolutional neural networks; hardware-software co-design; accelerator simulator; inference accelerator;
D O I：
10.1109/isocc47750.2019.9027697
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Tiling techniques and bit quantization are one of the popular optimization methods for designing convolutional neural networks (CNNs) inference accelerators as they provide extremely high efficiency for limited hardware resources. In this paper, we present a simulator for designing CNN accelerator using these optimization techniques. The simulator provides intermediate and final results that support development of the design strategy for accuracy-guaranteed bit-width and dynamic fixed point with user defined tiling factor.
引用
收藏
页码：283 / 284
页数：2
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