Design of a comparator in a 0.25 μm CMOS technology.

被引：0

作者：

van Bakel, N ^{[1
]}

van den Brand, J ^{[1
]}

Verkooijen, H ^{[1
]}

Schmelling, M ^{[1
]}

Sexauer, E ^{[1
]}

机构：

[1] Free Univ Amsterdam, NIKHEF H, NL-1098 SJ Amsterdam, Netherlands

来源：

PROCEEDINGS OF THE SIXTH WORKSHOP ON ELECTRONICS FOR LHC EXPERIMENTS | 2000年 / 2000卷 / 10期

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A comparator for the LHCb readout chip, the Beetle, has been designed in a 0.25 mum CMOS technology and is sent for fabrication. To improve threshold uniformity, each comparator has a 3 bits DAC. The comparator can handle positive and negative input signals. A polarity signal changes the polarity of the threshold level and makes the output signal always active high. The output signal is latched by a 40MHz clock and is selectable between time-over-threshold mode (in 25ns bins) and one pulse mode (25ns). Simulation results will be discussed in section II.

引用

页码：525 / 529

页数：5