Minimal digital chaotic system

被引：25

作者：

Nepomuceno, Erivelton G. ^{[1
]}

Lima, Arthur M. ^{[1
]}

Arias-Garcia, Janier ^{[2
]}

Perc, Matjaz ^{[3
,4
,5
]}

Repnik, Robert ^{[3
]}

机构：

[1] Univ Fed Sao Joao del Rei, Control & Modelling Grp GCOM, Dept Elect Engn, BR-36307352 Sao Joao Del Rei, MG, Brazil

[2] Univ Fed Minas Gerais, Dept Elect Engn, Belo Horizonte, MG, Brazil

[3] Univ Maribor, Fac Nat Sci & Math, Koroska Cesta 160, SI-2000 Maribor, Slovenia

[4] Univ Maribor, CAMTP, Mladinska 3, SI-2000 Maribor, Slovenia

[5] Complex Sci Hub Vienna, Josefstadterstr 39, A-1080 Vienna, Austria

来源：

CHAOS SOLITONS & FRACTALS | 2019年 / 120卷

关键词：

Chaos; Nonlinear dynamics; FPGA synthesis; Computer arithmetic; Digital system;

D O I：

10.1016/j.chaos.2019.01.019

中图分类号：

O1 [数学];

学科分类号：

0701 ; 070101 ;

摘要：

Over the past few decades, many works have been devoted to designing simple chaotic systems based on analog electronic circuits. However, the same attention is not observed in digital chaotic systems. This paper presents a design of a digital chaotic system using a digit complement. This special case of fixed-point number representation allows us to reduce the silicon area and the number of logic elements to perform the arithmetic operations. The design presents a configurable number of bits, and it is based on the logistic map. The proposed circuit has been implemented on a reconfigurable hardware, FPGA Cyclone V, showing that the number of logic elements has been significantly reduced compared to other works in the literature. (C) 2019 Elsevier Ltd. All rights reserved.

引用

页码：62 / 66

页数：5

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