Low Energy Mapping Techniques under Reliability and Bandwidth Constraints

被引：2

作者：

Masi, Marina ^{[1
]}

Mineo, Andrea ^{[1
]}

Palesi, Maurizio ^{[2
]}

Ascia, Giuseppe ^{[1
]}

Catania, Vincenzo ^{[1
]}

机构：

[1] Univ Catania, I-95124 Catania, Italy

[2] Kore Univ, Enna, Italy

来源：

2013 IEEE 15TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS & 2013 IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND UBIQUITOUS COMPUTING (HPCC_EUC) | 2013年

关键词：

ON-CHIP; NETWORKS; AWARE;

D O I：

10.1109/HPCC.and.EUC.2013.300

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The energy consumed by the links of a Network-on-Chip (NoC) accounts for a significant fraction of the overall energy budget in a multi/many-core system. Reducing voltage of the links allows to save energy but at the cost of an increase of the bit error rate (BER). Since different communications might have different reliability (i.e., BER) requirements, in this paper we present a new mapping technique aimed at optimising the static allocation of the tasks into the nodes of the NoC and determining the optimal link voltage swing for minimising the energy consumption under bandwidth and reliability constraints.

引用

页码：2088 / 2095

页数：8

共 41 条

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