Wafer level Cu-Cu direct bonding for 3D integration

被引:39
作者
Kim, Sarah Eunkyung [1 ]
Kim, Sungdong [2 ]
机构
[1] Seoul Natl Univ Sci & Technol, Grad Sch NID Fus Technol, Seoul 139743, South Korea
[2] Seoul Natl Univ Sci & Technol, Dept Mech Syst Design Engn, Seoul 139743, South Korea
基金
新加坡国家研究基金会;
关键词
3D IC; Wafer-to-wafer; Wafer level stacking; Warpage; Thermo-compression bonding;
D O I
10.1016/j.mee.2014.12.012
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Wafer level bonding and stacking process for 3D stacked IC was proposed and technical issues were discussed. Cu bumps surrounded by recessed SiO2 were thermo-compression bonded and electrically evaluated using Kelvin structures. Defects at the bonding interface such as voids were responsible for electrical resistance distribution. Wafer alignment during stacking process was found to be affected by several factors like non-uniform bump height, the spacers in a bonding fixture and wafer warpage. Step by step warpage measurement revealed that the wafer warpage was dependent on process steps and worsened at bonding step. (C) 2014 Elsevier B.V. All rights reserved.
引用
收藏
页码:158 / 163
页数:6
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