A Two-Stage Rate Control Mechanism for RDO-Based H.264/AVC Encoders

被引:6
作者
Chang, Li-Chuan [1 ]
Kuo, Chih-Hung [1 ]
Liu, Bin-Da [1 ]
机构
[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan
关键词
H.264/AVC; rate control; rate-distortion optimization;
D O I
10.1109/TCSVT.2011.2129770
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper jointly considers the mechanisms of rate control and the rate-distortion optimization (RDO) for the H.264/AVC hardware encoder. The proposed architecture performs intra prediction and inter prediction with our rate control mechanism in the first two stages. In addition, a low complexity macroblock (MB)-level mean absolute difference (MAD) prediction algorithm which considers both the motion information and the MAD value in the neighboring and current MBs is proposed. The proposed rate control algorithm can reduce the computational complexity and does not suffer from data dependency problems which may decrease the rate-distortion performance, thus it is suitable for H.264/AVC hardware encoders. Furthermore, the RDO-based architecture for the H.264/AVC encoder reduces the number of accurate rate-distortion cost calculators while maintaining the high rate-distortion performance. Experimental results show that the proposed rate control algorithm with the RDO-based architecture can improve the rate-distortion performance of H.264/AVC.
引用
收藏
页码:660 / 673
页数:14
相关论文
共 28 条
[1]   An efficient H.264 VLSI advanced video encoder [J].
Babionitakis, K. ;
Lentaris, G. ;
Nakos, K. ;
Reisis, D. ;
Vlassopoulos, N. ;
Doumenis, G. ;
Georgakarakos, G. ;
Sifnaios, J. .
2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, :545-+
[2]   A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications [J].
Chang, Hsiu-Cheng ;
Chen, Jia-Wei ;
Wu, Bing-Tsung ;
Su, Ching-Lung ;
Wang, Jinn-Shyan ;
Guo, Jiun-In .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2009, 19 (12) :1739-1754
[3]  
Chang LC, 2010, IEEE INT SYMP CIRC S, P661, DOI 10.1109/ISCAS.2010.5537501
[4]   2.8 to 67.2mW low-power and power-aware H.264 encoder for mobile applications [J].
Chen, Tung-Chien ;
Chen, Yu-Han ;
Tsai, Chuan-Yung ;
Tsai, Sung-Fang ;
Chien, Shao-Yi ;
Chen, Liang-Gee .
2007 Symposium on VLSI Circuits, Digest of Technical Papers, 2007, :222-223
[5]   Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder [J].
Chen, Tung-Chien ;
Chien, Shao-Yi ;
Huang, Yu-Wen ;
Tsai, Chen-Han ;
Chen, Ching-Yeh ;
Chen, To-Wei ;
Chen, Liang-Gee .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2006, 16 (06) :673-688
[6]   Quantization parameter refinement in H.264 through ρ-domain rate model [J].
Dong, Yutao ;
Fang, Xiangzhong ;
Yang, Jing .
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2008, E91D (06) :1834-1837
[7]   Overview of AVS video standard [J].
Fan, L ;
Ma, SW ;
Wu, F .
2004 IEEE INTERNATIONAL CONFERENCE ON MULTIMEDIA AND EXP (ICME), VOLS 1-3, 2004, :423-426
[8]  
GU JW, 2007, THESIS NATL TSING HU
[9]  
HASHIMOTO R, 2006, P INT S INT PROC COM, P618
[10]   Low-delay rate control for DCT video coding via ρ-domain source modeling [J].
He, ZH ;
Kim, YK ;
Mitra, SK .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2001, 11 (08) :928-940