GA Based Selective Harmonic Elimination for Multilevel Inverter with Reduced Number of Switches

被引：0

作者：

Karaca, Hulusi ^{[1
]}

Bektas, Enes ^{[2
]}

机构：

[1] Selcuk Univ, Fac Technol, Dept Elect & Elect Engn, TR-42075 Konya, Turkey

[2] Univ Cankin Karatekin, Fac Engn & Architecture, Dept Elect & Elect Engn, Cankiri, Turkey

来源：

WORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE, WCECS 2015, VOL I | 2015年

关键词：

Genetic algorithm; minimum number of switches; multilevel inverter; selective harmonic elimination; total harmonic distortion;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Multilevel inverters have been used in the power applications to get low total harmonic distortion (THD) in medium or high voltage levels. In order to get low THD in the output voltage, several techniques have been applied to multilevel inverter. One of these techniques is Selective Harmonic Elimination (SHE) that has an extensive research area in the field of power electronics. It is also an alternative to usual PWM techniques and includes nonlinear equations of stepped voltage waveform. In this paper, multilevel inverter with reduced number of switches which enables a reduction in the system cost has been proposed, and solution of SHE equations have been optimized by Genetic Algorithm (GA). The results of simulation and analysis have apparently proved that proposed GA based SHE technique eliminates desired harmonic order.

引用

页码：204 / 209

页数：6

共 50 条

[31] A New Multilevel Inverter with Fewer Number of Control Switches
Pachagade, Ruchi M.
Ranjana, Mahajan Sagar Bhaskar
Maroti, Pandav Kiran
Maheshwari, Ruchita
2015 CONFERENCE ON POWER, CONTROL, COMMUNICATION AND COMPUTATIONAL TECHNOLOGIES FOR SUSTAINABLE GROWTH (PCCCTSG), 2015, : 246 - U568
[32] Cascaded Half-Bridge Multilevel Inverter with Reduced Number of Power Switches
Jahan, Hossein Khoun
Shotorbani, Amin Mohammadpour
Abapour, Mehdi
Zare, Kazem
Blaabjerg, Frede
Yang, Yongheng
2018 IEEE 4TH SOUTHERN POWER ELECTRONICS CONFERENCE (SPEC), 2018,
[33] Investigation and validation of PV fed reduced switch asymmetric multilevel inverter using optimization based selective harmonic elimination technique
Jayakumar, T.
Ramani, G.
Jamuna, P.
Ramraj, B.
Chandrasekaran, Gokul
Maheswari, C.
Stonier, Albert Alexander
Peter, Geno
Ganji, Vivekananda
AUTOMATIKA, 2023, 64 (03) : 441 - 452
[34] A Novel Multilevel Inverter with Reduced Number of Switches Using Simplified PWM Technique
Chavali P.S.
Rao P.V.R.
Vani M.U.
Journal of The Institution of Engineers (India): Series B, 2020, 101 (03) : 203 - 216
[35] A Symbiotic Organism Search-Based Selective Harmonic Elimination in a Switched Capacitor Multilevel Inverter
Kumari, Manita
Sarwar, Adil
Tariq, Mohd
Ahmad, Shafiq
Shah Noor Mohamed, Adamali
Rodrigues, Eduardo M. G.
ENERGIES, 2022, 15 (01)
[36] A novel design and performance improvement of symmetric multilevel inverter with reduced switches using genetic algorithm
Ponraj, Ram Prakash
Sigamani, Titus
SOFT COMPUTING, 2021, 25 (06) : 4597 - 4607
[37] Three-Phase Multilevel Inverter Using Selective Harmonic Elimination with Marine Predator Algorithm
Riad, Nancy
Anis, Wagdy
Elkassas, Ahmed
Hassan, Abd El-Wahab
ELECTRONICS, 2021, 10 (04) : 1 - 21
[38] Multi Carrier PWM and Selective Harmonic Elimination technique for Cascade Multilevel Inverter
Gupta, Hemant
Yadav, Arvind
Maurya, Sanjay
PROCEEDINGS OF THE 2016 IEEE 2ND INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRICAL & ELECTRONICS, INFORMATION, COMMUNICATION & BIO INFORMATICS (IEEE AEEICB-2016), 2016, : 98 - 102
[39] Reconfigurable Selective Harmonic Elimination Technique for Wide Range Operations in Asymmetric Cascaded Multilevel Inverter
Kavitha, R.
Thottungal, Rani
JOURNAL OF POWER ELECTRONICS, 2018, 18 (04) : 1037 - 1050
[40] Experimental validation of a modular multilevel inverter with less number of switches
Thakre, Kishor
Mohanty, Kanungo Barada
Kommukuri, Vinaya Sagar
Chatterjee, Aditi
2016 NATIONAL POWER SYSTEMS CONFERENCE (NPSC), 2016,

← 1 2 3 4 5 →