GA Based Selective Harmonic Elimination for Multilevel Inverter with Reduced Number of Switches

被引:0
|
作者
Karaca, Hulusi [1 ]
Bektas, Enes [2 ]
机构
[1] Selcuk Univ, Fac Technol, Dept Elect & Elect Engn, TR-42075 Konya, Turkey
[2] Univ Cankin Karatekin, Fac Engn & Architecture, Dept Elect & Elect Engn, Cankiri, Turkey
来源
WORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE, WCECS 2015, VOL I | 2015年
关键词
Genetic algorithm; minimum number of switches; multilevel inverter; selective harmonic elimination; total harmonic distortion;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Multilevel inverters have been used in the power applications to get low total harmonic distortion (THD) in medium or high voltage levels. In order to get low THD in the output voltage, several techniques have been applied to multilevel inverter. One of these techniques is Selective Harmonic Elimination (SHE) that has an extensive research area in the field of power electronics. It is also an alternative to usual PWM techniques and includes nonlinear equations of stepped voltage waveform. In this paper, multilevel inverter with reduced number of switches which enables a reduction in the system cost has been proposed, and solution of SHE equations have been optimized by Genetic Algorithm (GA). The results of simulation and analysis have apparently proved that proposed GA based SHE technique eliminates desired harmonic order.
引用
收藏
页码:204 / 209
页数:6
相关论文
共 50 条
  • [21] Novel Asymmetrical Multilevel Inverter Topology with Reduced Number of Switches for Photovoltaic Applications
    Mudadla, Dhananjaya
    Sandeep, N.
    Rao, G. Rama
    2015 INTERNATIONAL CONFERENCE ON COMPUTATION OF POWER, ENERGY, INFORMATION AND COMMUNICATION (ICCPEIC), 2015, : 123 - 128
  • [22] Design and simulation of cascaded and hybrid multilevel inverter with reduced number of semiconductor switches
    Pradhan, Ajoya Kumar
    Kar, Sanjeeb Kumar
    Mohanty, Mahendra Kumar
    Behra, Navneet
    INTERNATIONAL JOURNAL OF AMBIENT ENERGY, 2021, 42 (08) : 950 - 960
  • [23] Real-time control of Selective Harmonic Elimination in a Reduced Switch Multilevel Inverter with unequal DC sources
    Bektas, Yasin
    AIN SHAMS ENGINEERING JOURNAL, 2024, 15 (06)
  • [24] A new strategy in selective harmonic elimination for a photovoltaic multilevel inverter
    Mohammadalizadeh, Soroush
    Ghayeni, Mohsen
    2016 4TH IRANIAN CONFERENCE ON RENEWABLE ENERGY & DISTRIBUTED GENERATION (ICREDG), 2016, : 50 - 55
  • [25] Selective Harmonic Elimination of Cascaded H-Bridge Multilevel Inverter using Genetic Algorithm
    Chatterjee, Aniruddho
    Rastogi, Adarsh
    Rastogi, Rajat
    Saini, Ajay
    Sahoo, Sarat Kumar
    2017 INNOVATIONS IN POWER AND ADVANCED COMPUTING TECHNOLOGIES (I-PACT), 2017,
  • [26] Multilevel selective harmonic elimination PWM technique in the nine level voltage inverter
    Khoukha, Imarazene
    Hachemi, Chekireb
    El Madjid, Berkouk
    2007 INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING & SYSTEMS: ICCES '07, 2007, : 387 - +
  • [27] Application of swarm optimisation-based modified algorithm for selective harmonic elimination in reduced switch count multilevel inverter
    Panda, Kaibalya Prasad
    Panda, Gayadhar
    IET POWER ELECTRONICS, 2018, 11 (08) : 1472 - 1482
  • [28] Runge Kutta optimization-based selective harmonic elimination in an H-bridge multilevel inverter
    Sajid, Injila
    Sarwar, Adil
    Tariq, Mohd
    Bakhsh, Farhad Ilahi
    Hussan, Md Reyaz
    Ahmad, Shafiq
    Mohamed, Adamali Shah Noor
    Ahmad, Akbar
    IET POWER ELECTRONICS, 2023, 16 (11) : 1849 - 1865
  • [29] Single Phase Symmetrical and Asymmetrical Design of Multilevel Inverter Topology with Reduced Number of Switches
    Siddique, Marif Daula
    Mustafa, Asif
    Sarwar, Adil
    Mekhilef, Saad
    Shah, Noraisyah Binti Mohamed
    Seyedamahmousian, Mehdi
    Stojcevski, Alex
    Horan, Ben
    Ogura, Koki
    2018 IEEMA ENGINEER INFINITE CONFERENCE (ETECHNXT), 2018,
  • [30] Novel symmetric and asymmetric topology of multilevel inverter with reduced number of switches
    Reddy, Kelam Bala Muralidhar
    Pattnaik, Swapnajit
    2017 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT), 2017, : 165 - 170