The asynchronous counterflow pipeline bit-serial multiplier

We propose a novel architecture of an asynchronous bit-serial multiplier with counterflow data streams. The crucial idea of the proposed design is that data transfer between basic cells is acknowledged by another data transfer in the opposite direction. This design solution has resulted in lower hardware complexity because there is no extra acknowledge circuitry. For the multiplier design, a mixed-mode delay model is adopted. First, the control circuit of the multiplier's basic cell is designed as a speed-independent circuit. Then the method for interconnecting basic cells into a 1D array is presented. Finally, we incorporate data-path function into the basic cell under the bounded-delay model.