Automated optimized overlay sampling for high-order processing in double patterning lithography

被引：5

作者：

Koay, Chiew-seng ^{[1
]}

Colburn, Matthew E. ^{[1
]}

Izikson, Pavel ^{[2
]}

Robinson, John C. ^{[3
]}

Kato, Cindy ^{[4
]}

Kurita, Hiroyuki ^{[4
]}

Nagaswami, Venkat ^{[3
]}

机构：

[1] IBM Corp, 257 Fuller Rd, Albany, NY 12303 USA

[2] KLA Tencor Israel, IL-23100 Migdal Haemak, Israel

[3] KLA Tencor Corp, Milpitas, CA 95035 USA

[4] KLA Tencor Japan Ltd, Hodogaya Ku, Yokohama, Kanagawa 2400005, Japan

来源：

METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXIV | 2010年 / 7638卷

关键词：

overlay; metrology; sampling; double patterning;

D O I：

10.1117/12.846371

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A primary concern when selecting an overlay sampling plan is the balance between accuracy and throughput. Two significant inflections in the semiconductor industry require even more careful sampling consideration: the transition from linear to high order overlay control, and the transition to dual patterning lithography (DPL) processes. To address the sampling challenges, an analysis tool in KT-Analyzer has been developed to enable quantitative evaluation of sampling schemes for both stage-grid and within-field analysis. Our previous studies indicated (1) the need for fully automated solutions that takes individual interpretation from the optimization process, and (2) the need for improved algorithms for this automation; both of which are described here.

引用

页数：10