A VLSI implementation of lifting-based forward and inverse wavelet transform

被引：0
|
作者：
Liu Leibo [1 ]
Zhang Milin [1 ]
Meng Hongying [1 ]
Zhang Li [1 ]
Wang Zhihua [1 ]
机构：
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
CHINESE JOURNAL OF ELECTRONICS | 2007年 / 16卷 / 03期
关键词：
DWT (discrete wavelet transform); lifting; SCLA (spatial combinative lifting algorithm);
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A VLSI architecture of Spatial combinative lifting algorithm (SCLA) based 2-D forward and inverse Discrete wavelet transform (DWT) with both 5/3, 9/7 filters and 5-level Mallat decomposition method is proposed in this paper. This processor is fabricated using UMC 0.18 mu m CMOS technology in a 1.5mm x 1.5mm die, containing 28k gates plus 47kbits on-chip SRAM. Test shows this chip can process at 23.29 frames/s with image resolution up to 1920 x 1080 x 24 bits (YUV422 full color) under 100MHz, and consuming 50mW under a 1.8V power supply.
引用
收藏
页码：423 / 428
页数：6
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