Star-Type Architecture with Low Transmission Latency for a 2D Mesh NOC

被引:0
|
作者
Chen, Kuan-Ju [1 ]
Peng, Chin-Hung [1 ]
Lai, Feipei [1 ]
机构
[1] Natl Taiwan Univ, Dept Comp Sci & Informat Engn, Dept Elect Engn, Grad Inst Biomed Elect & Bioinformat, Taipei 10617, Taiwan
来源
PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS) | 2010年
关键词
Network on chip; star type; mesh; low latency; deadlock-free;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The 2D mesh network on chip (NOC) is a popular NOC topology because of network scalability and the use of a simple routing algorithm. However, the long distance traffic may suffer from high transmission latency. In this paper, we propose an improved design called the star-type architecture in which the long distance traffic is allowed to traverse an additional second-level mesh. Simulation results demonstrate that the proposed design can reduce the number of hops traversed for long distance traffic. A 12 x 12 star-type NOC shows performance improvements of 17.2% and 10.3% in comparison with the normal 2D mesh and level-2 mesh architectures, respectively.
引用
收藏
页码:915 / 918
页数:4
相关论文
共 50 条
  • [21] An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures
    Sodring, Thomas
    Solheim, Ashild Gronstad
    Skeie, Tor
    Reinemo, Sven-Arne
    11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS, 2008, : 173 - 178
  • [22] VLSI architecture for hierarchical 2D mesh representation for very low bit rate applications
    Badawy, W
    Zhang, GQ
    Bayoumi, M
    42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1999, : 77 - 80
  • [23] Energy Efficient and High Performance Modified Mesh based 2-D NoC Architecture
    Reddy, B. Naresh Kumar
    Kar, Subrat
    2021 IEEE 22ND INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE SWITCHING AND ROUTING (IEEE HPSR), 2021,
  • [24] 基于2D Mesh拓扑结构的NoC模拟器设计
    乐建亮
    现代计算机, 2010, (03) : 139 - 144
  • [25] Efficient Memory Access in 2D Mesh NoC Architectures using High Bandwidth Routers
    Heisswolf, Jan
    Bischof, Simon
    Rueckauer, Michael
    Becker, Juergen
    2013 26TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2013), 2013,
  • [26] A Novel Reconfiguration Strategy for 2D Mesh-based NoC Faulty Core Tolerance
    Zhang, Ji-Yuan
    Fu, Fang-Fa
    Wu, Zi-Xu
    Yang, Chun-Guang
    Wang, Jin-Xiang
    2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 690 - 692
  • [27] 基于2D Mesh拓扑结构的NoC模拟器设计
    乐建亮
    现代计算机(专业版), 2010, (03) : 139 - 144
  • [28] 一种不规则2D Mesh的NoC路由算法
    徐欣
    王长山
    计算机与现代化, 2010, (05) : 111 - 114
  • [29] Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization
    Marcon, Cesar
    Fernandes, Ramon
    Cataldo, Rodrigo
    Grando, Fernando
    Webber, Thais
    Benso, Ana
    Poehls, Leticia B.
    2014 27TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2014 13TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID 2014), 2014, : 228 - 233
  • [30] Low-latency pipelined 2D and 3D CORDIC processors
    Antelo, Elisardo
    Villalba, Julio
    Zapata, Emilio L.
    IEEE TRANSACTIONS ON COMPUTERS, 2008, 57 (03) : 404 - 417