Development of a CMOS 310Mb/s receiver for free space optical wireless links

This paper presents the design and implementation of a CMOS 310Mb/s receiver for use in a multi-channel 155Mb/s Manchester-coded optical wireless link. The receiver consists of a pre-amplifier followed by a post amplifier circuit. Tile pre-amplifier is a three stage transimpedance amplifier with an NMOS load at the output of each stage to control gain and stability. To allow tile sensitivity of tile performance to key parameters to be visualized a nomograph technique was developed. The contours of the nomograph show how DC bias, dominant pole frequency and the gain of each stage vary with transistor dimensions. This allows the designer to select transistor sizes for a given bit rate and for stable operation. The design has been optimized to achieve -30dBm sensitivity at a BER of 10(-9) The post amplifier consists of a differential amplifier followed by a chain of inverters with feedback and produces rail-to-rail output swing. The design utilizes a replica biasing circuit which automatically biases title first amplification stage and provides an intrinsic high pass transfer function to attenuate 1/f receiver noise. The need for external filtering for the receiver is eliminated by this feature. The design is being realized in a 0.7 micron commodity mixed signal CMOS process by Alcatel Microelectronics.