Design and analysis of SHE-assisted STT MTJ/CMOS logic gates

被引：9
作者：
Barla, Prashanth [1 ]
Joshi, Vinod Kumar [1 ]
Bhat, Somashekara [1 ]
机构：
[1] Manipal Acad Higher Educ, Manipal Inst Technol, Dept Elect & Commun Engn, Manipal 576104, India
来源：
JOURNAL OF COMPUTATIONAL ELECTRONICS | 2021年 / 20卷 / 05期
关键词：
Magnetic tunnel junction; Spin-hall effect; Spin transfer torque; Nonvolatile; Logic-in-memory; HIGH-SPEED; FLIP-FLOP; SPIN; POWER; MEMORY; ANISOTROPY; SPINTRONICS; CIRCUITS; PROPOSAL; DEVICE;
D O I：
10.1007/s10825-021-01759-8
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We have investigated the spin-Hall effect (SHE)-assisted spin transfer torque (STT) switching mechanism in a three-terminal MTJ device developed using p-MTJ (perpendicular magnetic tunnel junction) and heavy metal materials of high atomic number, which possesses large spin-orbit interaction. Using p-MTJ schematic and complementary-metal-oxide-semiconductor (CMOS) logic, we have designed three basic hybrid logic-in-memory structure-based logic gates NOR/OR, NAND/AND, and XNOR /XOR. Then the performances of these hybrid gates are evaluated and the results are compared with the conventional CMOS-based gates in terms of power, delay, power delay product, and device count. From the analysis, it is concluded that SHE-assisted STT MTJ/CMOS logic gates are nonvolatile, consume less power, and occupy a smaller die area as compared to conventional CMOS only logic gates.
引用
收藏
页码：1964 / 1976
页数：13
相关论文
共 78 条
[1]   Fully Nonvolatile and Low Power Full Adder Based on Spin Transfer Torque Magnetic Tunnel Junction With Spin-Hall Effect Assistance [J].
Amirany, Abdolah ;
Rajaei, Ramin .
IEEE TRANSACTIONS ON MAGNETICS, 2018, 54 (12)
[2]  
An Q., 2017, ARITHMETIC LOGIC UNI, DOI 10.1109/NEWCAS.2017.8010169
[3]  
An Q, 2015, IEEE INT SYMP NANO, P163, DOI 10.1109/NANOARCH.2015.7180606
[4]  
Bandyopadhyay S., 2015, Introduction to Spintronics, V2nd
[5]   A novel self write-terminated driver for hybrid STT-MTJ/CMOS LIM structure [J].
Barla, Prashanth ;
Joshi, Vinod Kumar ;
Bhat, Somashekara .
AIN SHAMS ENGINEERING JOURNAL, 2021, 12 (02) :1839-1847
[6]   Spintronic devices: a promising alternative to CMOS devices [J].
Barla, Prashanth ;
Joshi, Vinod Kumar ;
Bhat, Somashekara .
JOURNAL OF COMPUTATIONAL ELECTRONICS, 2021, 20 (02) :805-837
[7]   Design and Analysis of LIM Hybrid MTJ/CMOS Logic Gates [J].
Barla, Prashanth ;
Shet, Deeksha ;
Joshi, Vinod Kumar ;
Bhat, Somashekara .
2020 5TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS' 20), 2020, :41-45
[8]   A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit [J].
Barla, Prashanth ;
Joshi, Vinod Kumar ;
Bhat, Somashekara .
IEEE ACCESS, 2020, 8 :6876-6889
[9]  
Behin-Aein B, 2010, NAT NANOTECHNOL, V5, P266, DOI [10.1038/nnano.2010.31, 10.1038/NNANO.2010.31]
[10]   Emission of spin waves by a magnetic multilayer traversed by a current [J].
Berger, L .
PHYSICAL REVIEW B, 1996, 54 (13) :9353-9358
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