Impact of Source-to-Gate and Drain-to-Gate Overlap Lengths on Performance of Inverted Staggered a-IGZO TFTs With an Etch Stopper

We report a comprehensive study on the impact of source-to-gate (L-S) and drain-to-gate (L-D) overlap lengths on the performance of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) employing the inverted staggered structure with an etch stopper (ES). Although drain current (I-D) is found to marginally decrease with increasing L-S, it is found to considerably increase with L-D. With the help of technology computer-aided design (TCAD) simulations, the increase in I-D with L-D is attributed to backchannel formation in the region beneath the drain, while the decrease in I-D with increasing L-S is attributed to the depletion of carriers from the backchannel in the region beneath the source. In addition, the threshold voltage (V-TH) shifts negatively with increasing L-D and drain voltage (V-D). All these effects are more pronounced in short channel TFTs than long channel TFTs, which could be the origin of the anomalous dependence of V-TH of the ES-type a-IGZO TFTs on channel length.