Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

被引:4
作者
Li Jin [1 ]
Liu Hong-Xia [1 ]
Li Bin [1 ]
Cao Lei [1 ]
Yuan Bo [1 ]
机构
[1] Xidian Univ, Key Lab Wide Bandgap Semicond Devices, Minist Educ, Sch Microelect, Xian 710071, Peoples R China
基金
中国国家自然科学基金;
关键词
strained-Si; gate stack double-gate MOSFETs; short channel effect; the drain-induced barrier-lowering; THRESHOLD-VOLTAGE MODEL; SOI; TECHNOLOGY; CHANNEL; SI;
D O I
10.1088/1674-1056/19/10/107302
中图分类号
O4 [物理学];
学科分类号
0702 ;
摘要
Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.
引用
收藏
页数:7
相关论文
共 14 条
[1]   A new analytical threshold voltage model for symmetrical double-gate MOSFETs with high-k gate dielectrics [J].
Chiang, T. K. ;
Chen, M. L. .
SOLID-STATE ELECTRONICS, 2007, 51 (03) :387-393
[2]   A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs [J].
Djeffal, F. ;
Meguellati, M. ;
Benhaya, A. .
PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES, 2009, 41 (10) :1872-1877
[3]   A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs [J].
Kumar, M. Jagadesh ;
Venkataraman, Vivek ;
Nawal, Susheel .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (10) :2500-2506
[4]   Advanced SOI p-MOSFETs with strained-Si channel on SiGe-on-insulator substrate fabricated by SIMOX technology [J].
Mizuno, T ;
Sugiyama, N ;
Kurobe, A ;
Takagi, S .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (08) :1612-1618
[5]   Strained SiCMOS (SS CMOS) technology: opportunities and challenges [J].
Rim, K ;
Anderson, R ;
Boyd, D ;
Cardone, F ;
Chan, K ;
Chen, H ;
Christansen, S ;
Chu, J ;
Jenkins, K ;
Kanarsky, T ;
Koester, S ;
Lee, BH ;
Lee, K ;
Mazzeo, V ;
Mocuta, A ;
Mocuta, D ;
Mooney, PM ;
Oldiges, P ;
Ott, J ;
Ronsheim, P ;
Roy, R ;
Steegen, A ;
Yang, M ;
Zhu, H ;
Ieong, M ;
Wong, HSP .
SOLID-STATE ELECTRONICS, 2003, 47 (07) :1133-1139
[6]   Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect [J].
Sharma, Rupendra Kumar ;
Gupta, Mridula ;
Gupta, R. S. .
SUPERLATTICES AND MICROSTRUCTURES, 2009, 45 (03) :91-104
[7]   The threshold voltage of SiC Schottky barrier source/drain MOSFET [J].
Tang Xiao-Yan ;
Zhang Yi-Men ;
Zhang Yu-Ming .
ACTA PHYSICA SINICA, 2009, 58 (01) :494-497
[8]   Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs [J].
Taur, Y .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (12) :2861-2869
[9]   A logic nanotechnology featuring strained-silicon [J].
Thompson, SE ;
Armstrong, M ;
Auth, C ;
Cea, S ;
Chau, R ;
Glass, G ;
Hoffman, T ;
Klaus, J ;
Ma, ZY ;
Mcintyre, B ;
Murthy, A ;
Obradovic, B ;
Shifren, L ;
Sivakumar, S ;
Tyagi, S ;
Ghani, T ;
Mistry, K ;
Bohr, M ;
El-Mansy, Y .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (04) :191-193
[10]   Compact analytical threshold-voltage model of nanoscale fully depleted strained-Si on silicon-germanium-on-insulator (SGOI) MOSFETs [J].
Venkataraman, Vivek ;
Nawal, Susheel ;
Kumar, M. Jagadesh .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (03) :554-562