A Broadband Differential Cascode Power Amplifier in 45 nm CMOS for High-Speed 60 GHz System-on-Chip

被引：20

作者：

Abbasi, Morteza ^{[1
]}

Kjellberg, Torgil ^{[1
,2
]}

de Graauw, Anton ^{[3
]}

van der Heijden, Edwin ^{[3
]}

Roovers, Raf ^{[3
]}

Zirath, Herbert ^{[1
]}

机构：

[1] Chalmers Univ Technol, Microwave Elect Lab, S-41296 Gothenburg, Sweden

[2] Chalmers Ind Technol, Gothenburg, Sweden

[3] NXP Semicond Res, Eindhoven, Netherlands

来源：

2010 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS RFIC SYMPOSIUM | 2010年

关键词：

60; GHz; power amplifier; 45nm CMOS; cascode; isolated P-well;

D O I：

10.1109/RFIC.2010.5477384

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A compact two-stage differential cascode power amplifier is designed and fabricated in 45 nm standard LP CMOS. The cascode configuration, with the common gate device placed in a separate P-well, provides reliable operating condition for the devices. The amplifier shows 20 dB small-signal gain centered at 60 GHz with a flat frequency response and 1-dB bandwidth of 10 GHz. The broadband large-signal operation is also ensured by providing constant load resistance to both stages over the entire band and coupling them with a dual resonance matching network. The chip delivers 11.2 dBm output power at 1-dB compression and up to 14.5 dBm power in saturation. The power amplifier operates with 2 V supply and draws 90 mA total current which results in 14.4% maximum PAE. The output third order intercept point is measured to be 18 dBm for two-tone measurement at 60 GHz with 0.5 GHz, 1 GHz and 2 GHz frequency separations.

引用

页码：533 / 536

页数：4

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