On the reconfiguration algorithm for fault-tolerant VLSI arrays

被引：0
作者：
Wu, JG [1 ]
Thambipillai, S [1 ]
机构：
[1] Nanyang Technol Univ, Ctr High Performance Embedded Syst, Singapore 639798, Singapore
来源：
COMPUTATIONAL SCIENCE - ICCS 2003, PT III, PROCEEDINGS | 2003年 / 2659卷
关键词：
degradable VLSI array; reconfiguration; fault-tolerance; greedy algorithm; NP-completeness;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
In this paper, an improved algorithm is presented for the NP-complete problem of reconfiguring a two-dimensional degradable VLSI array under the row and column routing constraints. The proposed algorithm adopts the partial computing for the logical row exclusion so that the most efficient algorithm, cited in literature, is speeded up without loss of performance. In addition, a flaw in the earlier approach is also addressed. Experimental results show that our algorithm is approximately 50% faster than the above stated algorithm.
引用
收藏
页码：360 / 366
页数：7
相关论文
共 50 条
  • [41] A genetic algorithm for fault-tolerant system design
    Echtle, K
    Eusgeld, I
    DEPENDABLE COMPUTING, 2003, 2847 : 197 - 213
  • [42] Fault-tolerant routing, reconfiguration and backward error recovery for parallel systems
    Bieker, B
    Deconinck, G
    Maehle, E
    Vounckx, J
    COMPUTER SYSTEMS SCIENCE AND ENGINEERING, 1997, 12 (04): : 245 - 253
  • [43] Preprocessing of Scenarios for Fast and Efficient Routing Reconfiguration in Fault-Tolerant NoCs
    Silveira, Jarbas
    Marcon, Cesar
    Cortez, Paulo
    Barroso, Giovanni
    Ferreira, Joao M.
    Mota, Rafael
    23RD EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP 2015), 2015, : 404 - 411
  • [44] A Fault-Tolerant Approach for Modular Robots through Self-Reconfiguration
    Qi, Jian
    Lai, Mingzhu
    Yang, Zhiyuan
    Zhao, Ning
    Han, Kai
    Sui, Xin
    Zhao, Jie
    Zhu, Yanhe
    ADVANCED INTELLIGENT SYSTEMS, 2024, 6 (07)
  • [45] Reconfiguration Algorithm for Low Temperature Sub-array on VLSI/WSI Arrays with Faults
    Jigang, Wu
    Niu, Zhipeng
    Zhu, Yuanbo
    Srikanthan, Thambipillai
    Shen, Qingni
    2011 18TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2011,
  • [46] Novel Bio-Inspired Approach for Fault-Tolerant VLSI Systems
    Samie, Mohammad
    Dragffy, Gabriel
    Tyrrell, Andy M.
    Pipe, Tony
    Bremner, Paul
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (10) : 1878 - 1891
  • [47] Stigmergic approaches applied to flexible fault-tolerant digital VLSI architectures
    Pani, Danilo
    Raffo, Luigi
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 2006, 66 (08) : 1014 - 1024
  • [48] Fault-tolerant embedding of linear arrays and rings in the star graph
    Latifi, S
    Bagherzadeh, N
    Gajjala, RR
    COMPUTERS & ELECTRICAL ENGINEERING, 1997, 23 (02) : 95 - 107
  • [49] Tight Upper Bound for Accelerating Reconfiguration of VLSI Arrays
    Wu, Jigang
    Han, Xiaogang
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2015, 24 (07)
  • [50] Realization of Fault-Tolerant Home Network Management Middleware with the TMO Structuring Approach and an Integration of Fault Detection and Reconfiguration Mechanisms
    Kim, K. H.
    Zhou, Qian
    Qian, Jing
    Moon, Kyung-Deok
    Park, Jun Hee
    Son, Young-Sung
    Lee, Chang-Eun
    Ku, Tai-Yeon
    PROCEEDINGS OF THE 12TH IEEE INTERNATIONAL SYMPOSIUM ON OBJECT/COMPONENT/SERVICE-ORIENTED REAL-TIME DISTRIBUTED COMPUTING, 2009, : 188 - +
12345